Current complementary metal oxide semiconductor (CMOS) technology uses silicides as contacts to source/drain (S/D) regions of devices that are fabricated upon a Si-containing substrate. Examples of silicides with low resistivity and contact resistance that are currently being used are the C54 phase of TiSi2, CoSi2, and NiSi. All three of these silicides are integrated using a self-aligned silicide process (i.e., a salicide process). This process consists of a blanket deposition of the metal (Ti, Co, or Ni) with a cap layer (such as TiN, Ti or W), annealing at a first lower temperature to form a first silicide phase (i.e., the C49 phase of TiSi, CoSi, or NiSi), selectively wet etching the cap layer and unreacted metal that is not in contact with silicon, and annealing at a second higher temperature to form the low resistance metal silicide phase (the C54 phase of TiSi2 or CoSi2). For the low resistance NiSi, the second anneal is typically not needed.
An additional approach for the Ni silicide is to form a metal rich Ni silicide during the first anneal followed by the formation of NiSi during the second anneal. One advantage of these particular suicides is that they all may be implemented with the self-aligned process avoiding additional lithographic steps.
In recent years, there has been a desire in the semiconductor industry to use different substrates besides Si-containing substrates in an attempt to improve the device performance by providing substrates that have increased electron/hole mobilities. One such substrate is a Ge-containing substrate.
One problem associated with Ge-containing substrates is that it is difficult to form contacts to Ge-containing substrates because germanium oxide is soluble in water. For example, a Ge wafer will be etched in a simple peroxide solution as the peroxide can both oxidize the germanium and dissolve the oxide. As a result, any metal-germanium or metal-silicon-germanium contact formed on a Ge substrate is more subject to being attacked by etching solutions. Thus, because the Ge concentration in the substrate is rising, the industry needs to modify the etching solutions to the new material. In general, solutions are much less aggressive and the percentage of water in them is reduced. The disadvantage to modifying etching solutions is that there is a fair amount of development needed in order to have the modification become incorporated into standard CMOS processing. Moreover, modified etch solutions equate to alterations in the present processing tools and recipes.
In view of the above, there is a need for providing an alternative technique for forming a germano-silicide contact directly atop a Ge-containing substrate that avoids the need to modify the current etching solutions, tools and recipes employed in the semiconductor industry.